There are many circuits where very precise measurements must be made in a short amount of time. One such circuit is the analog to digital A/D converter which is well known in the art. Fully differential analog-to-digital converters handle both the positive and the negative portions of the analog wave form and convert the analog signal into a digital word having a certain number of bits. Ideally, a fully differential A/D converter should have an infinite common mode rejection ratio (CMRR). However, due to practical limitations, such as the finite CMRR of the comparator, differing devices and parasitic capacitance, typical CMRR of an A/D converter is limited to about 50 db. A new topography is discussed in U.S. Pat. No. 4,803,462 of Hester and Dewit dated Feb. 6, 1989. The aforementioned application, which is hereby incorporated by reference herein, shows a circuit arrangement which increases the CMRR to the 70 db range.
Further study has revealed that to reduce the ratio even further the parasitic capacitance problem must be overcome. This problem is many fold in that the capacitance is ever changing and can be dependent upon circuit components, their aging, or even the humidity or temperature of the day. Thus, the target is a moving one.
Accordingly, there is a need in the art for a circuit arrangement which compensates for parasitic capacitance and which can do so even if such capacitance changes from time to time.